1. Field of the Invention
The present invention relates to a semiconductor device and manufacturing methods therefor. More particularly, the present invention relates to a semiconductor device with epitaxial source-drain extension regions and a manufacturing method therefor.
2. Description of the Related Art
Nowadays, millions of semiconductor devices are integrated together to construct very large scale integrated circuits.
FIG. 1 shows a sectional view of a conventional semiconductor device (transistor). A transistor typically comprises a gate dielectric layer 140 on a semiconductor substrate (not shown for conciseness) and a gate layer 150 on the gate dielectric layer 140, the transistor has first and second sidewall spacers 160, 165 formed on the sidewalls of the gate dielectric layer 140 and the gate layer 150. Commonly, the transistor also comprises a pair of source/drain regions 110 aligned with the peripheral borders of the second sidewall spacers 165. Further, a pair of source/drain extension regions 120 is formed within the surface region of the semiconductor substrate, extending beneath the gate dielectric layer 140 and the gate layer 150. A channel region 130 is formed in the semiconductor substrate between the pair of extension regions 120 and beneath the gate dielectric layer 140.
With the continuing reduction of characteristic dimensions of transistors, it is desired for the source/drain extension regions 120 to have a shallow junction depth in order to reduce area junction capacitance (Cjunc). Also, it is desired for the source/drain extension regions 120 to have a high activated dopant concentration to reduce accumulation resistance (Racc) and thus increase the transistor driving current.
To achieve the above objects, commonly, annealing, especially laser melting/sub-melting annealing, is applied to the source/drain extension regions formed through ion implantation.
However, it has been found by the inventors of the present invention through intensive research that there is still a need to improve junction depth and activated dopant concentration for the source/drain extension regions 120 formed through ion implantation and laser melting/sub-melting annealing. However, while SIMS (Secondary Ion Mass Spectrometry) is often used to measure dopant distribution after laser melting/sub-melting annealing, SIMS is unable to identify whether a dopant is activated.
Therefore, it has been recognized by the inventors of the present invention that there is a need for a semiconductor device having a shallow junction depth (or a small thickness) for the source/drain extension regions and a high activated dopant concentration, as well as a manufacturing method for manufacturing such a semiconductor device.